Supply clock generation (driver) circuit for 2PASCL
نویسندگان
چکیده
The paper presents a new quasi adiabatic logic family that uses two complementary split-level sinusoidal power supply clock for digital low power applications such as sensors. The proposed two-phase adiabatic static CMOS logic circuit (2PASCL) is using the principle of energy recovery and adiabatic switching. It has switching activity that is lower than dynamic logic and can be directly derived from static CMOS circuits. We have simulated the clock generation circuit using SPICE and investigate the most suitable scheme and highest energy efficiency for the energy recovery power supply/clocks.
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Supply clock generation (driver) circuit for 2PASCL: Hara active inductor equivalent circuit and simulation
Abstract The paper presents a split-level sinusoidal power supply clock generator circuit for Two-Phase Adiabatic Static CMOS Logic circuit (2PASCL). The driving of adiabatic logic requires adiabatic controlled sources of voltage. We study the clock voltage generator circuit using SPICE simulation and investigate the most suitable scheme and highest energy efficiency for the energy recovery pow...
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